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Qualcomm Hexagon TOSA operator matrix

This matrix records the TOSA 1.0 floating-point surface validated on Snapdragon X126100, Hexagon HTP v73, driver 30.0.222.0, and QAIRT 2.49.0.260730. “HTP” means the checked-in numerical fixture passed through the QNN HTP backend; “portable” means lowering is also covered without the SDK. The floating target admits FP16, BOOL conditions/results, and required INT32 indexing results. The separate integer target remains limited to INT8 IDENTITY and zero-point-aware INT8 MATMUL with INT32 output.

TOSA operatorQNN representationValidated restrictionEvidence
ARGMAXArgMaxFP16 input, INT32 output, one static axis, keep_dims=falseportable + HTP
MAX_POOL2DGather + ElementWiseMaximumFP16 NHWC, positive static kernel/stride, zero paddingportable + HTP
MATMULMatMulFP16, or exact INT8/INT32 tier; no transposeportable + HTP
CLAMPReluMinMaxFP16 bounds, NaN propagateportable + HTP
ERFnoneblocked: QAIRT 2.49 public QnnOpDef.h defines no ERF operationparity exception
SIGMOIDSigmoidFP16portable + HTP
TANHTanhFP16portable + HTP
ADDElementWiseAddFP16 broadcastingportable + HTP
LOGICAL_ANDElementWiseAndBOOLportable + HTP
LOGICAL_ORElementWiseOrBOOLportable + HTP
LOGICAL_XORElementWiseXorBOOLportable + HTP
MAXIMUMElementWiseMaximumFP16 broadcasting, NaN propagateportable + HTP
MINIMUMElementWiseMinimumFP16 broadcasting, NaN propagateportable + HTP
MULElementWiseMultiplyFP16 broadcasting, validated zero shiftportable + HTP
POWElementWisePowerFP16 broadcasting; TOSA domain requirement remains caller-visibleportable + HTP
SUBElementWiseSubtractFP16 broadcastingportable + HTP
ABSElementWiseAbsFP16portable + HTP
CEILElementWiseCeilFP16portable + HTP
COSElementWiseCosFP16, 8-ULP oracle boundportable + HTP
EXPElementWiseExpFP16portable + HTP
FLOORElementWiseFloorFP16portable + HTP
LOGElementWiseLogpositive FP16 fixture domainportable + HTP
LOGICAL_NOTElementWiseNotBOOLportable + HTP
NEGATEElementWiseNegFP16, zero input/output zero pointsportable + HTP
RECIPROCALElementWiseUnary(RECIPROCAL)nonzero FP16 fixture domainportable + HTP
RSQRTElementWiseRsqrtpositive FP16 fixture domainportable + HTP
SINElementWiseSinFP16, 8-ULP oracle boundportable + HTP
SELECTElementWiseSelectBOOL condition, FP16 valuesportable + HTP
EQUALElementWiseEqualFP16 input, BOOL outputportable + HTP
GREATERElementWiseGreaterFP16 input, BOOL outputportable + HTP
GREATER_EQUALElementWiseGreaterEqualFP16 input, BOOL outputportable + HTP
REDUCE_MAXReduceMaxFP16, one static axis, keep_dims=trueportable + HTP
REDUCE_MINReduceMinFP16, one static axis, keep_dims=trueportable + HTP
REDUCE_PRODUCTGather + ElementWiseMultiplyFP16, one static axis; public ReduceProd rejected by HTP v73portable + HTP
REDUCE_SUMReduceSumFP16, one static axis, keep_dims=trueportable + HTP
CONCATConcatFP16, static valid axisportable + HTP
RESHAPEReshapeFP16, compile-time CONST_SHAPEportable + HTP
REVERSEdescending static indices + GatherFP16, one static valid axisportable + HTP
TRANSPOSETransposeFP16, static complete permutationportable + HTP
CONSTowned QNN static tensorinternal FP16 constants with exact byte lengthportable + HTP
CONST_SHAPEconsumed during loweringstatic valid reshape shapeportable + HTP
IDENTITYReshapeFP16 or exact INT8 tierportable + HTP

Every attribute, dtype, rank, axis, permutation, shape, and constant payload first passes the shared bounded TOSA verifier and semantic analyzer. The Hexagon planner then owns constants, uses checked shape/byte arithmetic, and rejects unsupported graphs before entering QNN. The native bridge repeats descriptor arity, pointer, element-size, constant-size, reference, and generated-tensor resource checks before calling the provider.

Reproduce the portable and hardware evidence with the commands in the Hexagon README.